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Project Coordinator


 

Dr Georg Stettinger

 
Infineon Technologies AG
81726 München
Germany

Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation

Endri Kaja, Nicolas Gerlin, Monideep Bora, Gabriel Rutsch, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker

Abstract: Safety-critical designs need to ensure reliable operations even under a hostile working environment with a certain degree of confidence. Continuous technology scaling has resulted in designs being more susceptible to the risk of failure. As a result, the safety requirements are constantly evolving and becoming more stringent. For validating and measuring the robustness of safety-critical designs, fault injection methods are employed within the design flows. To ensure safety requirements’ compliance, and at the same time to cope with the ever-increasing complexity of modern SoCs, the existing design flows become inadequate as the process is repetitive, time-tedious, and requires high manual efforts. In this paper, a fully automated, fast and accurate, fault emulation framework based on the FPGA platform is proposed that enables a high level of controllability and observability for fault injection. The approach uses model-driven engineering concepts and automates various fault injection campaigns, namely, statistical fault injection (SFI), direct fault injection (DFI), and exhaustive fault injection (EFI). A novel design architecture tailored for the FPGA platform is also proposed to improve the overall productivity of performing fault emulation. The proposed approach scales to a wide variety of RISC-V based CPU subsystems with varying complexity in size and features. The experimental results demonstrate a significant gain in the fault emulation performance by a factor of 2.75x to 47.57x when compared to the standard simulation-based fault injection methods..


Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation


 

Acknowledgement

ArchitectECA2030 has been accepted for funding within (ECSEL JU) in collaboration with the European Union’s H2020 Framework Programs under grant agreement No 877539.

The project will receive an ECSEL JU funding up to 4 M€ completed with national budgets from national funding authorities in Germany, Netherlands, Czech Republic, Austria and Norway.  

Project Facts

Short Name: ArchitectECA2030

Full Name: Trustable architectures with acceptable residual risk for the electric, connected and automated cars

Duration:  01/07/2020- 30/06/2023

Total Costs: ~ € 13,6 Mio.

Consortium: 20 partners from 8 countries

Coordinator: Infineon Technologies AG

Funding

 

Horizon 2020
Horizon 2020

 

    

National Funding

National Funding

 


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